Papilio.Hardware History

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* RS232 Serial Port
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* 4096 Color VGA
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* VGA Port - 4r,4g,4b, 4096 Color, 12-bit VGA Output
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* VGA Port - 4r,4g,4b VGA Output
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* VGA Port - 4r,4g,4b, 4096 Color, 12-bit VGA Output
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[[LogicStart Shield|LogicStart Shield Hardware Guide]]
\\
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->[[Computing Shield]][[<<]]
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->[[ClassicComputingShield|Computing Shield]][[<<]]
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!!!Specifications
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[[ClassicComputingShield|Computing Shield Hardware Guide]]
\\
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->[[http://retrocade.gadgetfactory.net/index.php?n=Main.RetroCadeMegaWing|RetroCade MegaWing]][[<<]]
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!!![[ClassicComputingShield|Computing Shield]]
The Classic Computing Shield provides all of the hardware needed to recreate classic computing systems on the Papilio DUO.
%%
%rframe width=375% http://www.gadgetfactory.net/images/shieldsWikiPics/CC/Classic-Computing-Shield.jpg
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!!!Specifications
!!!Specifications
* 4096 Color VGA
* 2 Stereo Audio Jacks
* Two PS/2 Jacks
* 2 Atari Style Joystick Ports
* MicroSD Socket
* 4 Directional Control Buttons
[[<<]]

[[LogicStart Shield|LogicStart Shield Hardware Guide]]
\\
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!Papilio Shields
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The Open Source [[PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the %newwin%[[http://retrocade.gadgetfactory.net|RetroCade Synth]] and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.
to:
The LogicStart Shield provides everything needed to get started with VHDL and FPGA development on the Papilio with one convenient and easy to connect circuit board.
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* Xilinx Spartan 6 LX9 FPGA
* 64Mbit (8MByte) SDRAM
* High Speed USB port for programming and communication
* %newwin%[[http:
//www.alvie.com/zpuino/index.html|ZPUino Soft Processor]]
* YM2149
* MOS 6581 (I.E. C64 SID)[[<<]]
************[[http://store.gadgetfactory.net/papilio-pro/|'''Buy at Gadget Factory''']]
\\
[[Papilio DUO
Hardware Guide]]
to:
!!!Specifications
* 7 Segment Display - 4 Character
* VGA Port - 4r,4g,4b VGA Output
* Stereo Audio Jack - 1
/8" Jack, Low Pass Filter
* 4 Directional Buttons
* 6 Analog Channels connected to ATmega32U4 on Papilio DUO
* 8 LED's - User Feedback
* 8 Slide Switches - User Input
* Snap off the VGA portion of the circuit to free up two 8-bit Wing Slots[[<<]]

[[LogicStart Shield|LogicStart Shield
Hardware Guide]]
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[[#Section5|Shields]][[<<]]
->[[Computing Shield]][[<<]]
->[[LogicStart Shield]][[<<]]
->[[http://retrocade.gadgetfactory.net/index.php?n=Main.RetroCadeMegaWing|RetroCade MegaWing]][[<<]]
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----
[[#Section5]]
!!![[LogicStart Shield]]
The Open Source [[PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the %newwin%[[http://retrocade.gadgetfactory.net|RetroCade Synth]] and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.
%%
%rframe width=375% [[PapilioPro|Attach:ppro.jpg]]
\\
\\
\\

* Xilinx Spartan 6 LX9 FPGA
* 64Mbit (8MByte) SDRAM
* High Speed USB port for programming and communication
* %newwin%[[http://www.alvie.com/zpuino/index.html|ZPUino Soft Processor]]
* YM2149
* MOS 6581 (I.E. C64 SID)[[<<]]
************[[http://store.gadgetfactory.net/papilio-pro/|'''Buy at Gadget Factory''']]
\\
[[Papilio DUO Hardware Guide]]
\\
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->[[Main.RetroCadeMegaWing|RetroCade MegaWing]][[<<]]
to:
->[[http://retrocade.gadgetfactory.net/index.php?n=Main.RetroCadeMegaWing|RetroCade MegaWing]][[<<]]
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->[[RetroCade MegaWing]][[<<]]
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->[[Main.RetroCadeMegaWing|RetroCade MegaWing]][[<<]]
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->[[PapilioDUOHardwareGuide|Papilio DUO]][[<<]]
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->[[Arcade MegaWing]][[<<]]
->[[LogicStart MegaWing]][[<<]]
->[[RetroCade MegaWing]][[<<]]
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%rframe width=375% [[PapilioDUOHardwareGuide|Attach:pduo.gif]]
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%rframe width=375% [[PapilioDUOHardwareGuide|Attach:pduo.gif]]
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%rframe width=375% [[https://s3.amazonaws.com/ksr/assets/002/039/417/573d5f99a50962f0ba436ab0129389b3_large.gif?1400692873]]
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!!![[PapilioDUOHardwareGuide|Papilio DUO Hardware Guide]]
The Papilio DUO has an FPGA on the top and the same chip that is used in the Arduino Leonardo (ATmega32U4) on the bottom. It's like having an Arduino with a full circuit laboratory connected to it! For example, you can draw circuits to move pins, connect extra serial ports, or connect a bitcoin miner to the Arduino-Compatible chip. Just plug it into your computer using a USB cable, download our software and start drawing your own circuits.
%%
%rframe width=375% [[PapilioDUOHardwareGuide|Attach:pduo.jpg]]
%rframe width=375% [[PapilioDUOHardwareGuide|https://s3.amazonaws.com/ksr/assets/002/039/417/573d5f99a50962f0ba436ab0129389b3_large.gif?1400692873]]
\\
\\
\\

* Xilinx Spartan 6 LX9 FPGA
* 512KB or 2MB SRAM
* AVR ATmega32U4 chip that is a derivative of the Arduino Leonardo design.
* High efficiency LTC3419 Switching Voltage Regulator
* 64Mbit Macronix MX25L6445 SPI Flash
* 54 I/O pins arranged in an Arduino-Compatible Mega Form Factor
* High Speed USB port for programming and communication
* %newwin%[[http://www.alvie.com/zpuino/index.html|ZPUino Soft Processor]]
[[<<]]
\\
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to:
[[Papilio DUO Hardware Guide]]
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(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic, Arduino:)
to:
(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic, Arduino, papillon:)
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(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic:)
to:
(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic, Arduino:)
May 29, 2013, at 03:53 PM by Jack Gassett -
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>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#General|Papilio FPGA]][[<<]]
->[[Papilio One]][[<<]]
->[[Papilio Pro]][[<<]]
[[#Section3|MegaWings]][[<<]]
[[#Section4|Wings]][[<<]]
>><<
\\
May 23, 2013, at 11:38 AM by Jack Gassett -
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>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#General|Papilio FPGA]][[<<]]
->[[Papilio One]][[<<]]
->[[Papilio Pro]][[<<]]
[[#Section3|MegaWings]][[<<]]
[[#Section4|Wings]][[<<]]
>><<
May 10, 2013, at 05:36 PM by Jack Gassett -
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\\
May 10, 2013, at 04:41 PM by Jack Gassett -
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The Open Source [[Main.PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the %newwin%[[http://retrocade.gadgetfactory.net|RetroCade Synth]] and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.
to:
The Open Source [[PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the %newwin%[[http://retrocade.gadgetfactory.net|RetroCade Synth]] and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.
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>><<
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>><<
May 10, 2013, at 04:40 PM by Jack Gassett -
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\\
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||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board with Xilinx Spartan 3E
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board with Xilinx Spartan 6 LX9 and SDRAM
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>><<
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>><<
May 10, 2013, at 04:38 PM by Jack Gassett -
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!!![[Papilio One]]
to:
!!![[Papilio One|Papilio One Hardware Guide]]
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!!![[PapilioPro|Papilio Pro LX9]]
to:
!!![[PapilioPro|Papilio Pro Hardware Guide]]
May 10, 2013, at 04:37 PM by Jack Gassett -
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(:title Papilio One Hardware:)
to:
(:title Papilio Hardware Index:)
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!!Papilio Hardware
to:
!!Papilio Hardware Index
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*Fully Assembled with a Xilinx XC3S500E and 4Mbit SPI Flash Memory
to:
*Fully Assembled with a Xilinx Spartan 3E and 4Mbit SPI Flash Memory
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!!![[Main.PapilioPro|Papilio Pro LX9]]
to:
!!![[PapilioPro|Papilio Pro LX9]]
May 10, 2013, at 04:35 PM by Jack Gassett -
Deleted lines 22-25:

The Papilio One is a powerful, open-source, expandable development board perfect for the design and prototyping of your unique ideas. You can customize the capabilities of the Papilio with snap-on modular expansions called Wings (similar to Arduino shields) which provide added functionality to the board, and simultaneously expand the creative possibilities!

Choose the Papilio One with the Xilinx Spartan 3E FPGA chip, providing a plentiful amount of digital logic to quickly get your prototyping off the ground. Or, for even more power, go with the Papilio Pro for the Xilinx Spartan 6 FPGA and 64Mb of SDRAM! You can code for the FPGA using established development tools, or you can use Gadget Factory's custom Arduino IDE to easily write Arduino code and upload it to the AVR8 soft processor!
Changed lines 26-27 from:
The RetroCade MegaWing provides all of the audio hardware needed to make sweet retro music in one convenient and easy to connect circuit board. It snaps into the Papilio Pro and gives it the necessary hardware resources to communicate with the outside world.
to:
The Papilio One is a powerful, open-source, expandable development board perfect for the design and prototyping of your unique ideas. You can customize the capabilities of the Papilio with snap-on modular expansions called Wings (similar to Arduino shields) which provide added functionality to the board, and simultaneously expand the creative possibilities!

At its heart, the Papilio One has a Xilinx Spartan 3E FPGA chip, providing a plentiful amount of digital logic to quickly get your prototyping off the ground
. In addition, you can code for the FPGA using established development tools, or you can use Gadget Factory's custom Arduino IDE to easily write Arduino code and upload it to the AVR8 soft processor!
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48 I/O lines!
to:
*48 I/O lines!
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***[[http://store.gadgetfactory.net/index.php?main_page=product_info&cPath=12&products_id=59|'''Available soon for $54.99 at Gadget Factory''']]
Changed lines 49-50 from:
The Open Source [[Main.PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the RetroCade Synth and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.
to:
The Open Source [[Main.PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the %newwin%[[http://retrocade.gadgetfactory.net|RetroCade Synth]] and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.
%%
May 10, 2013, at 04:32 PM by Jack Gassett -
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[[#General]]
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[[#General]]
!!Papilio Hardware
May 10, 2013, at 04:31 PM by Jack Gassett -
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>>round frame<<
Have you been thinking about jumping into FPGA development but are not sure how to get started? Well, take a look at the Papilio - an Open Source FPGA board with everything you need to get started at a low price. With a [[https://store-wgbxee.mybigcommerce.com/forum.gadgetfactory.net|friendly and supportive community]], [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34|free VHDL eBook]], [[http://forum.gadgetfactory.net/index.php?/files/file/8-papilio-arduino-ide/|Open Source Arduino compatible Soft Processors]], and [[http://forum.gadgetfactory.net/index.php?/page/articles.html|plenty of code examples]] you will have all the resources needed to get you started on the FPGA path. It's never been easier to jump into the wide-open world of FPGA development!

The Papilio One is a powerful, open-source, expandable development board perfect for the design and prototyping of your unique ideas. You can customize the capabilities of the Papilio with snap-on modular expansions called Wings (similar to Arduino shields) which provide added functionality to the board, and simultaneously expand the creative possibilities!

Choose the Papilio One with the Xilinx Spartan 3E FPGA chip, providing a plentiful amount of digital logic to quickly get your prototyping off the ground. Or, for even more power, go with the Papilio Pro for the Xilinx Spartan 6 FPGA and 64Mb of SDRAM! You can code for the FPGA using established development tools, or you can use Gadget Factory's custom Arduino IDE to easily write Arduino code and upload it to the AVR8 soft processor!
>><<
Added lines 18-25:
>><<

>>round frame<<
Have you been thinking about jumping into FPGA development but are not sure how to get started? Well, take a look at the Papilio - an Open Source FPGA board with everything you need to get started at a low price. With a [[https://store-wgbxee.mybigcommerce.com/forum.gadgetfactory.net|friendly and supportive community]], [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34|free VHDL eBook]], [[http://forum.gadgetfactory.net/index.php?/files/file/8-papilio-arduino-ide/|Open Source Arduino compatible Soft Processors]], and [[http://forum.gadgetfactory.net/index.php?/page/articles.html|plenty of code examples]] you will have all the resources needed to get you started on the FPGA path. It's never been easier to jump into the wide-open world of FPGA development!

The Papilio One is a powerful, open-source, expandable development board perfect for the design and prototyping of your unique ideas. You can customize the capabilities of the Papilio with snap-on modular expansions called Wings (similar to Arduino shields) which provide added functionality to the board, and simultaneously expand the creative possibilities!

Choose the Papilio One with the Xilinx Spartan 3E FPGA chip, providing a plentiful amount of digital logic to quickly get your prototyping off the ground. Or, for even more power, go with the Papilio Pro for the Xilinx Spartan 6 FPGA and 64Mb of SDRAM! You can code for the FPGA using established development tools, or you can use Gadget Factory's custom Arduino IDE to easily write Arduino code and upload it to the AVR8 soft processor!
May 10, 2013, at 04:30 PM by Jack Gassett -
Added lines 10-16:
>>round frame<<
Have you been thinking about jumping into FPGA development but are not sure how to get started? Well, take a look at the Papilio - an Open Source FPGA board with everything you need to get started at a low price. With a [[https://store-wgbxee.mybigcommerce.com/forum.gadgetfactory.net|friendly and supportive community]], [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34|free VHDL eBook]], [[http://forum.gadgetfactory.net/index.php?/files/file/8-papilio-arduino-ide/|Open Source Arduino compatible Soft Processors]], and [[http://forum.gadgetfactory.net/index.php?/page/articles.html|plenty of code examples]] you will have all the resources needed to get you started on the FPGA path. It's never been easier to jump into the wide-open world of FPGA development!

The Papilio One is a powerful, open-source, expandable development board perfect for the design and prototyping of your unique ideas. You can customize the capabilities of the Papilio with snap-on modular expansions called Wings (similar to Arduino shields) which provide added functionality to the board, and simultaneously expand the creative possibilities!

Choose the Papilio One with the Xilinx Spartan 3E FPGA chip, providing a plentiful amount of digital logic to quickly get your prototyping off the ground. Or, for even more power, go with the Papilio Pro for the Xilinx Spartan 6 FPGA and 64Mb of SDRAM! You can code for the FPGA using established development tools, or you can use Gadget Factory's custom Arduino IDE to easily write Arduino code and upload it to the AVR8 soft processor!
>><<
May 10, 2013, at 04:24 PM by Jack Gassett -
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!!![[Papilio One]]
The RetroCade MegaWing provides all of the audio hardware needed to make sweet retro music in one convenient and easy to connect circuit board. It snaps into the Papilio Pro and gives it the necessary hardware resources to communicate with the outside world.

%lframe width=450% [[PapilioOne|Attach:pone.jpg]]
\\
\\
\\


*Fully Assembled with a Xilinx XC3S500E and 4Mbit SPI Flash Memory
*Provides an Easy Introduction to FPGA, Digital Electronics, and System on a Chip design
*Easily add New Functionality with Wings that Snap onto the Board
*Two-Channel USB Connection for JTAG and Serial Communications
*Four Independent Power Rails at 5V, 3.3V, 2.5V, and 1.2V
*Power Supplied by a Power Connector or USB
*Input Voltage (recommended): 6.5-15V
48 I/O lines!
[[<<]]
***[[http://store.gadgetfactory.net/index.php?main_page=product_info&cPath=12&products_id=59|'''Available soon for $54.99 at Gadget Factory''']]
***[[http://store.gadgetfactory.net/papilio-one-500k/|'''Buy Papilio One 500K at Gadget Factory''']]
***[[http://store.gadgetfactory.net/papilio-one-250k/|'''Buy Papilio One 250K at Gadget Factory''']]
May 10, 2013, at 04:20 PM by Jack Gassett -
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||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board with Xilinx Spartan 3E
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board with Xilinx Spartan 6 LX9 and SDRAM
to:
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!!![[Main.PapilioPro|Papilio Pro LX9]]
The Open Source [[Main.PapilioPro|Papilio Pro LX9]] FPGA board is a powerful and flexible platform that provides the core for exciting projects such as the RetroCade Synth and the %newwin%[[http://arcade.gadgetfactory.net|Papilio Arcade]]. It acts as the empty canvas that classic audio chips and arcade motherboards can be recreated on. Its flexible nature means that it can be re-used with future %newwin%[[http://papilio.cc|Papilio]] projects by simply purchasing the [[http://papilio.cc/index.php?n=Papilio.MegaWings|MegaWing]] portion of a project.

%rframe width=375% [[PapilioPro|Attach:ppro.jpg]]
\\
\\
\\
\\
\\

* Xilinx Spartan 6 LX9 FPGA
* 64Mbit (8MByte) SDRAM
* High Speed USB port for programming and communication
* %newwin%[[http://www.alvie.com/zpuino/index.html|ZPUino Soft Processor]]
* YM2149
* MOS 6581 (I.E. C64 SID)[[<<]]
************[[http://store.gadgetfactory.net/papilio-pro/|'''Buy at Gadget Factory''']]

||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board with Xilinx Spartan 3E
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board with Xilinx Spartan 6 LX9 and SDRAM
May 10, 2013, at 04:13 PM by Jack Gassett -
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[[#General]]
||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board with Xilinx Spartan 3E
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board with Xilinx Spartan 6 LX9 and SDRAM
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[[#General]]
||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board with Xilinx Spartan 3E
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board with Xilinx Spartan 6 LX9 and SDRAM
to:
>><<
May 10, 2013, at 04:12 PM by Jack Gassett -
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>><<
May 10, 2013, at 04:11 PM by Jack Gassett -
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->[[#Section1|Papilio One]][[<<]]
[[#Section2|Papilio Pro]][[<<]]
to:
->[[Papilio One]][[<<]]
->[[Papilio Pro]][[<<]]
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||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board

----
[[#Section1]]
\\

----
[[#Section2]]
\\
to:
||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board with Xilinx Spartan 3E
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board with Xilinx Spartan 6 LX9 and SDRAM
May 10, 2013, at 04:07 PM by Jack Gassett -
Changed lines 20-21 from:
\\
to:
||%thumb%[[Papilio One|Attach:pone.jpg]]||[[Papilio One]] ||Papilio One FPGA Board
||%thumb%[[Papilio Pro|Attach:ppro.jpg]]||[[Papilio Pro]] ||Papilio Pro FPGA Board
May 10, 2013, at 04:00 PM by Jack Gassett -
Changed lines 12-23 from:
[[#Overview|Overview]][[<<]]
[[#Section1|Spartan 3E]][[<<]]
[[#Section2|Power]][[<<]]
[[#Section3|Dual Channel USB]][[<<]]
[[#Section4|SPI Flash]][[<<]]
[[#Section5|I/O]][[<<]]
[[#Section6|Oscillator]][[<<]]
[[#Section7|JTAG]][[<<]]
[[#Section8|LEDs]][[<<]]
[[#Links|Links]][[<<]]
[[#License|License]][[<<]]
[[#Images|Images
]][[<<]]
to:
[[#General|Papilio FPGA]][[<<]]
->[[#Section1|Papilio One]][[<<]]
[[#Section2|Papilio Pro]][[<<]]
[[#Section3|MegaWings]][[<<]]
[[#Section4|Wings]][[<<]]
Changed lines 19-59 from:
[[#Overview]]
!!Papilio One
>>round frame<<
The Papilio is an Open Source FPGA development board based on the
Xilinx Spartan 3E FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning [[Digital Electronics]].
>><<

>>round frame float:left width:400px bgcolor=#ffffff<<
%width=500%[[http://papilio.cc/uploads/Papilio/p1sparkfun.jpg|http://papilio.cc/uploads/Papilio/p1sparkfun.jpg]]
>><<
[[<<]]

!!!Features
>>lrindent round frame<<
!!! Power
* Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
* Power supplied by a power connector or USB.
* DC Input Jack.
** Input Voltage (recommended): 6.5-10V
!!! USB
* Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.
!!! Spartan 3E FPGA
* 32MHz oscillator that can be used by [[Papilio.DigitalClockManager|Xilinx's DCM to generate any required clock speed]].
* VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
* I/O can be set to support 1.2V, 2.5V, or 3.3V.
!!! SPI Flash
* 4M SPI Flash
!!! Wings
* 48 bidirectional I/O lines which can be split up as:
** 1x 32 Bit Wing or
** 3x 16 Bit Wings or
** 6x 8 Bit Wings
* .1" spacing for compatibility with bread boards.
!!! Dimensions
* 2.7"x2.7"
[[<<]]
>><<
to:
[[#General]]
\\
Deleted lines 23-48:
!!!Xilinx Spartan 3E
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:callout1.png
The [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Spartan 3E FPGA]] used in the Papilio One offers some exciting features:

'''Multi-Voltage'''
->With the VCCO Select header built into the Papilio voltages of 1.2V, 2.5V, and 3.3V can be used.

'''Digital Clock Manager (DCM)'''
->Easily generate any clock from 5Mhz to 300Mhz using the DCM clock wizard. 4 DCM's allow you to generate many clocks from the external 32Mhz Oscillator included on the Papilio One board.

%rframe text-align=center width=300px% [[Attach:schematic1.png|Attach:schematic1.png]]|'''FPGA Schematic'''

'''Multiple Signal Standards'''
->LVCMOS, LVTTL, HSTL, differential pairs for LVDS, mini-LVDS

'''Boot from SPI Flash'''
->The Spartan 3E boots from an industry standard SPI Flash device included on the Papilio One board.

'''BRAM Memory Blocks'''
->The Spartan 3E includes fast, dual-port, internal SRAM called Block RAM.

||class=prettytable3
||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
||Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)||
||Papilio One 500K||20||360Kbit (45KByte)||320Kbit (40KByte)||
||Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)
Deleted lines 25-30:
>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
>><<

[[<<]]
Changed lines 28-49 from:
!!!Power
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:callout2.png
The Papilio One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.

'''Power Selection'''
-> When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

-> When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

%rframe text-align=center width=350px% [[Attach:schematic2.png|Attach:schematic2.png]]|'''Power Schematic'''

'''Power Jack'''
* Input: 6-15V DC
* Current: Draws up to 800mA
* Size: 2.1mm
* Polarity: Positive Tip

'''RPAR'''
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].

[[<<]]
to:
\\
Changed lines 32-48 from:
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach
:usb-callout.png
The Papilio One uses the %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip for JTAG programming and Serial UART communications.

*Channel A is connected to the Papilio One in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio One and provides very fast programming of the FPGA (500mS
).
[[<<]]


%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
[[<<]]


|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P88||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P90||
to:
(:include Papilio.MegaWings :)
Changed lines 37-50 from:
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach
:flash-callout.png
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
The 4Mbit SST %newwin%[[http://ww1.microchip.com/downloads/en/DeviceDoc/25051A.pdf|SST25VF040B]] SPI Flash chip provides plenty of space for a boot bit file and user data. Any bit file written to SPI Flash using the [[Papilio.PapilioLoaderV2|Papilio Loader]] tool will automatically startup when power is applied.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective
)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||FLASH_CS||Output||SPI Flash Chip Select||N/A||N/A||P24||
||FLASH_CLK||Output||SPI Flash Clock||N/A||N/A||P50||
||FLASH_MOSI||Output||SPI Flash Master Out Slave In (MOSI)||N/A||N/A||P27||
||FLASH_MISO||Input||SPI Flash Master In Slave Out (MISO)||N/A||N/A||P44||
\\
to:
(:include Papilio.Wings :)
Deleted lines 38-141:
[[#Section5]]
!!!I/O
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
'''I/O Blocks'''
->The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
** 2 to 16 mA programmable output current drive strength.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.

'''I/O Banks'''
->The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

%rframe height=250px% [[Attach:schematic5.png|Attach:schematic5.png]]

[[<<]]

----
[[#Section6]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Digital Clock Manager (DCM). There are four [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P89||
\\

----
[[#Section7]]
!!!JTAG
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe width=200px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
The JTAG header on the Papilio One is provided so external JTAG programmers can be used:

'''Use a Xilinx Programming Cable'''
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||JTAG_TMS||Input||JTAG TMS||N/A||N/A||P75||
||JTAG_TCK||Input||JTAG TCK||N/A||N/A||P77||
||JTAG_SI||Input||JTAG SI||N/A||N/A||P100||
||JTAG_SO||Output||JTAG SO||N/A||N/A||P76||
\\

----
[[#Section8]]
!!!LED's
The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.

----
[[#Links]]
!!!Links
->'''Papilio One Design Files'''
-->[[http://forum.gadgetfactory.net/index.php?/files/file/2-papilio-one-generic-ucf/|Papilio One Generic User Constraint File (UCF)]]
-->[[http://forum.gadgetfactory.net/index.php?/files/file/13-eagle-files/|Papilio One EAGLE Design Files (License CC-BY-SA-NC)]]
-->[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Papilio One Schematic (PDF)]]

->'''Community Links'''
-->[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-one/|Papilio One Project Showcase]]
-->[[http://forum.gadgetfactory.net/index.php?/forum/89-papilio-one/|Papilio One Forum]]
-->[[http://forum.gadgetfactory.net/index.php?/files/category/3-papilio-one/|Papilio One Downloads]]

->'''Misc'''
-->[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]
-->[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[<<]]
----
[[#License]]
!!!License
(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio One is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
\\
Papilio One copyright Jack Gassett, Gadget Factory.
(:divend:)
[[<<]]

----
[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:PapilioOne.png|Attach:PapilioOne.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilioOne2.png|Attach:papilioOne2.png]]
>>postit<<
%notetitle% Papilio One%%

Click the images for full size hi-resolution views of the Papilio One.
>><<
[[<<]]

%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Attach:schematicall.png]]
>>postit<<
%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio One Schematic
>><<
[[<<]]
May 10, 2013, at 11:18 AM by Jack Gassett -
Changed lines 1-2 from:
(:title Papilio Hardware:)
to:
(:title Papilio One Hardware:)
Changed lines 8-13 from:
!! Papilio One Overview
>>lrindent round frame text-align=justify
<<
The Papilio is an Open Source FPGA development board based on the
Xilinx Spartan 3E FPGA (
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel
USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning
[[Digital Electronics]].
to:
>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#Section1|Spartan 3E]][[<<]]
[[#Section2|Power]][[<<]]
[[#Section3|Dual Channel
USB]][[<<]]
[[#Section4|SPI Flash]]
[[<<]]
[[#Section5|I/O]][[<<]]
[[#Section6|Oscillator]][[<<]]
[[#Section7|JTAG]][[<<]]
[[#Section8|LEDs]][[<<]]
[[#Links|Links]][[<<]]
[[#License|License]][[<<]]
[[#Images|Images]][[<<]]
Changed lines 26-27 from:
>>lrindent round frame bgcolor=#ffffff<<
%center%http://papilio.cc/uploads/Papilio/p1sparkfun.jpg
to:
[[#Overview]]
!!Papilio One
>>round frame
<<
The Papilio is an Open Source FPGA development board based on the
Xilinx Spartan 3E FPGA ([[http:
//www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning [[Digital Electronics]].
Changed lines 35-46 from:
!!Quick Links
[[http
://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications
to:
>>round frame float:left width:400px bgcolor=#ffffff<<
%width=500%
[[http://papilio.cc/uploads/Papilio/p1sparkfun.jpg|http://papilio.cc/uploads/Papilio/p1sparkfun.jpg]]
>><<
[[<<]]

!!!Features
>>lrindent round frame<<
Changed line 46 from:
** Input Voltage (recommended): 6.5-15V
to:
** Input Voltage (recommended): 6.5-10V
Changed line 55 from:
* 4M SPI Flash for [[design persistence]].
to:
* 4M SPI Flash
Changed lines 64-79 from:
!!! License
*
[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|All design files are available under a Completely Open Source Creative Commons Attribution Non-Commercial.]]

!!Inputs/Outputs
!!!I/O Blocks
The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
*Features
:
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18)
.
** 2 to 16 mA programmable output current drive strength
.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.
!!!I/O Banks
*The VCCO jumper selects the voltage for all of
the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

!! Power
to:
[[<<]]
>><<

----
[[#Section1]]
!!!Xilinx Spartan 3E
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:callout1.png
The [[http
://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Spartan 3E FPGA]] used in the Papilio One offers some exciting features:

'''Multi-Voltage'''
->With the VCCO Select header built into the Papilio voltages of 1.2V, 2
.5V, and 3.3V can be used.

'''Digital Clock Manager (DCM)'''
->Easily generate any clock from 5Mhz to 300Mhz using
the DCM clock wizard. 4 DCM's allow you to generate many clocks from the external 32Mhz Oscillator included on the Papilio One board.

%rframe text-align=center width=300px% [[Attach:schematic1
.png|Attach:schematic1.png]]|'''FPGA Schematic'''

'''Multiple Signal Standards'''
->LVCMOS, LVTTL, HSTL, differential pairs for LVDS, mini-LVDS

'''Boot from SPI Flash'''
->The Spartan 3E boots from an industry standard SPI Flash device included on the Papilio One board.

'''BRAM Memory Blocks'''
->The Spartan 3E includes fast, dual-port, internal SRAM called Block RAM.

||class=prettytable3
||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
||Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)||
||Papilio One 500K||20||360Kbit (45KByte)||320Kbit (40KByte)||
||Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)
\\

>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
>><<

[[<<]]

----
[[#Section2]]
!!!Power
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:callout2.png
Changed lines 109-120 from:
!!! Power Selection

When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

!!! RPAR

The JTAG programming pins on the Spartan 3E always operate at 2
.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].

!!! Power
Jack
to:
'''Power Selection'''
->
When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

-> When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

%rframe text-align=center width=350px% [[Attach:schematic2.png|Attach:schematic2.png]]|'''Power Schematic'''

'''Power
Jack'''
Changed lines 122-132 from:
!! Memory
The
on-board SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at start-up. Bitstreams are loaded to SPI Flash using the [[Papilio Loader]].

!! Communications
The Papilio One uses a [[http://www
.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FTDI 2232D]] USB chip which provides two channels over one USB connection. One of the channels is configured as a simple UART device and shows up as a virtual COM port. The other channel takes advantage of the MPSSE (Multi-Protocol Synchronous Serial Engine) functionality to implement a high speed JTAG channel for programming the [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan 3E]].
!!!Drivers
The first time
the Papilio One is plugged into the computer it will be necessary to install the FTDI device drivers. [[http://ftdichip.com/Drivers/D2XX.htm|Drivers can be downloaded from the FTDI website]].

!!!UART
When the Papilio One is plugged into the USB port both channels will be detected and will show up under
the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.
to:
'''RPAR'''
->The JTAG programming pins
on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].

[[<<]]

----
[[#Section3]]
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
The Papilio One uses the %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip for JTAG programming and Serial UART communications.

*Channel A is connected to the Papilio One in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio One and provides very fast programming of the FPGA (500mS).
[[<<]]


%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
[[<<]]


|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P88||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P90||
\\

----
[[#Section4]]
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:flash-callout.png
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
The 4Mbit SST %newwin%[[http://ww1.microchip.com/downloads/en/DeviceDoc/25051A.pdf|SST25VF040B]] SPI Flash chip provides plenty of space for a boot bit file and user data. Any bit file written to SPI Flash using the [[Papilio.PapilioLoaderV2|Papilio Loader]] tool will automatically startup when power is applied.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||FLASH_CS||Output||SPI Flash Chip Select||N/A||N/A||P24||
||FLASH_CLK||Output||SPI Flash Clock||N/A||N/A||P50||
||FLASH_MOSI||Output||SPI Flash Master Out Slave In (MOSI)||N/A||N/A||P27||
||FLASH_MISO||Input||SPI Flash Master In Slave Out (MISO)||N/A||N/A||P44||
\\

----
[[#Section5]]
!!!I/O
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
'''I/O Blocks'''
->The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
** 2 to 16 mA programmable output current drive strength.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.

'''I/O Banks'''
->The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

%rframe height=250px% [[Attach:schematic5.png|Attach:schematic5.png]]

[[<<]]

----
[[#Section6]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Digital Clock Manager (DCM). There are four [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P89||
\\

----
[[#Section7]]
Changed lines 199-214 from:
The Xilinx device is programmed using any application that can support the FT2232D MPSSE JTAG mode. The [[http://gadgetforge.gadgetfactory.net/gf/project/butterflyloader/|Papilio Loader]] is one such application.

!!!JTAG Programming Port
The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The
Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Papilio One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.

TEMPORARY LIMITATION: In order to use
the external JTAG port the FT2232D lines that are connected to the JTAG port need to be put into a HIGH-Z state. This has not been tested yet and will probably require a special application.

!!!EEPROM
Custom VID
/PID and configuration data can be loaded into the provided EEPROM using the [[http://ftdichip.com/Resources/Utilities.htm#MProg|FTDI MProg]] application.


!! Misc
!!! Oscillator
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a [[Papilio.DigitalClockManager
|Digital Clock Manager]]. The Spartan 3E provides 4 Digital Clock Managers.

!!! LED's
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe width=200px%
[[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
The JTAG header on the Papilio One is provided so external JTAG programmers can be used:

'''Use a Xilinx Programming Cable'''
->If you want to use the
Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||JTAG_TMS||Input||JTAG TMS
||N/A||N/A||P75||
||JTAG_TCK||Input||JTAG TCK||N/A||N/A||P77||
||JTAG_SI||Input||JTAG SI||N/A||N/A||P100||
||JTAG_SO||Output||JTAG SO||N/A||N/A||P76||
\\

----
[[#Section8]]
!!!LED's
Changed lines 221-225 from:
!! Additional information:
!!!Diagram
>>lrindent round frame bgcolor=#ffffff<<
%center%
http://www.gadgetfactory.net/images/pap1diag.png
>><<
to:
----
[[#Links]]
!!!Links
-
>'''Papilio One Design Files'''
-->[[
http://forum.gadgetfactory.net/index.php?/files/file/2-papilio-one-generic-ucf/|Papilio One Generic User Constraint File (UCF)]]
--
>[[http://forum.gadgetfactory.net/index.php?/files/file/13-eagle-files/|Papilio One EAGLE Design Files (License CC-BY-SA-NC)]]
--
>[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Papilio One Schematic (PDF)]]

->'''Community Links'''
-->[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-one/|Papilio One Project Showcase]]
-->[[http://forum.gadgetfactory.net/index.php?/forum/89-papilio-one/|Papilio One Forum]]
-->[[http://forum.gadgetfactory.net/index.php?/files/category/3-papilio-one/|Papilio One Downloads]]

->'''Misc'''
-->[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]
-->[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[
<<]]
----
[[#License]]
!!!License
(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio One is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
\\
Papilio One copyright Jack Gassett, Gadget Factory.
(:divend:)
[[<<]]

----
[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:PapilioOne.png|Attach:PapilioOne.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilioOne2.png|Attach:papilioOne2.png]]
>>postit<<
%notetitle% Papilio One%%

Click the images for full size hi-resolution views of the Papilio One.
>><<
[[<<]]

%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Attach:schematicall.png]]
>>postit<<
%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio One Schematic
>><<
[[<<]]
Changed line 17 from:
%center%http://www.gadgetfactory.net/images/Papilio_One_small.jpg
to:
%center%http://papilio.cc/uploads/Papilio/p1sparkfun.jpg
Added lines 52-53:
!!! Dimensions
* 2.7"x2.7"
Added line 9:
>>lrindent round frame text-align=justify<<
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>><<
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http://www.gadgetfactory.net/images/Papilio_One_small.jpg
----
to:
>>lrindent round frame bgcolor=#ffffff<<
%center%
http://www.gadgetfactory.net/images/Papilio_One_small.jpg
>><<
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----
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----
to:
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----
to:
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----
to:
Changed line 86 from:
----
to:
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----
to:
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----
to:
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http://www.gadgetfactory.net/images/pap1diag.png
to:
>>lrindent round frame bgcolor=#ffffff<<
%center%
http://www.gadgetfactory.net/images/pap1diag.png
>><<
Changed line 3 from:
(:keywords FPGA, Xilinx, Spartan 3E, Spartan 3A, Papilio platform, open source hardware, Wings, FPGA development, electronics, FPGA India, embedded processors, soft processors, ip cores, embedded processing, configurable logic, reconfigurable logic, download software, Papilio design, Papilio Explorer, Papilio Builder:)
to:
(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic:)
Changed line 1 from:
(:title Hardware:)
to:
(:title Papilio Hardware:)
Changed line 1 from:
(:title Papilio Hardware:)
to:
(:title Hardware:)
Added lines 1-6:
(:title Papilio Hardware:)

(:keywords FPGA, Xilinx, Spartan 3E, Spartan 3A, Papilio platform, open source hardware, Wings, FPGA development, electronics, FPGA India, embedded processors, soft processors, ip cores, embedded processing, configurable logic, reconfigurable logic, download software, Papilio design, Papilio Explorer, Papilio Builder:)

(:description Papilio platform is easy to use FPGA development platform for beginners and a powerful modular design environment for professional developers. Download Papiliio project sources, software, design files, support applications, libraries, Papilio Explorer, Papilio Builder IDE:)
June 12, 2011, at 05:12 PM by Jack Gassett -
Changed line 3 from:
The Papilio is a FPGA development board based on the
to:
The Papilio is an Open Source FPGA development board based on the
June 12, 2011, at 05:11 PM by Jack Gassett -
Added lines 43-44:
!!! License
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|All design files are available under a Completely Open Source Creative Commons Attribution Non-Commercial.]]
May 04, 2011, at 10:16 AM by Jack Gassett -
Changed line 50 from:
**Optionnal keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
to:
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
Changed line 106 from:
!! Aditionnal information:
to:
!! Additional information:
May 04, 2011, at 10:15 AM by Jack Gassett -
Changed line 8 from:
(:include Purchase:)
to:
http://www.gadgetfactory.net/images/Papilio_One_small.jpg
Changed lines 11-12 from:
(:include Papilio_Quick_Links:)
to:
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http
://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC
)]]
Deleted lines 21-23:
!! Diagram
http://www.gadgetfactory.net/images/pap1diag.png
----
Changed line 26 from:
* DC Input Jack
to:
* DC Input Jack.
Added lines 44-55:
!!Inputs/Outputs
!!!I/O Blocks
The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
*Features:
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optionnal keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
** 2 to 16 mA programmable output current drive strength.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.
!!!I/O Banks
*The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.
----
Deleted lines 64-67:
!!! I/O Bank Power Selection

The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.
Changed lines 105-108 from:
to:
----
!! Aditionnal information:
!!!Diagram
http://www.gadgetfactory.net/images/pap1diag.png
April 06, 2011, at 04:43 PM by David Strathman -
Deleted line 1:
! Papilio Hardware
April 06, 2011, at 04:43 PM by David Strathman -
Added line 1:
(:include HardwareHeader:)
Deleted line 2:
(:include HardwareHeader:)
April 01, 2011, at 02:39 PM by Jack Gassett -
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!! Overview
to:
!! Papilio One Overview
April 01, 2011, at 11:28 AM by Jack Gassett -
Changed line 15 from:
!!! Diagram
to:
!! Diagram
April 01, 2011, at 11:27 AM by Jack Gassett -
Added lines 15-17:
!!! Diagram
http://www.gadgetfactory.net/images/pap1diag.png
----
Deleted lines 93-94:
!!! Diagram
http://www.gadgetfactory.net/images/pap1diag.png
March 18, 2011, at 02:26 PM by Jack Gassett -
Changed lines 1-2 from:
! Papilio One Hardware
to:
! Papilio Hardware
(:include HardwareHeader:)
Changed line 51 from:
The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator.
to:
The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
Changed line 24 from:
* 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
to:
* 32MHz oscillator that can be used by [[Papilio.DigitalClockManager|Xilinx's DCM to generate any required clock speed]].
Changed line 85 from:
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a Digital Clock Manager. The Spartan 3E provides 4 Digital Clock Managers.
to:
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a [[Papilio.DigitalClockManager|Digital Clock Manager]]. The Spartan 3E provides 4 Digital Clock Managers.
Changed lines 88-91 from:
The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.
to:
The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.

!!! Diagram
http://www.gadgetfactory.net/images/pap1diag.png
Changed lines 31-33 from:
** 1 - 32 Bit Wing or
** 3 - 16 Bit Wings or
** 6 - 8 Bit Wings
to:
** 1x 32 Bit Wing or
** 3x 16 Bit Wings or
** 6x 8 Bit Wings
Changed line 28 from:
* 4M SPI Flash for design persistence.
to:
* 4M SPI Flash for [[design persistence]].
Changed lines 8-13 from:
The Papilio can be bought from the [[http://www.gadgetfactory.net | Gadget Factory store.]]

The Papilio One comes in two sizes:
* [[http://www.gadgetfactory.net/index.php?main_page=product_info&cPath=1&products_id=18 | Papilio One 250K]] - $49.99 in the store now.
* [[http://www.gadgetfactory.net/index.php?main_page=product_info&cPath=1&products_id=25 | Papilio One 500K]] - $74.99 in the store now.
to:
(:include Purchase:)
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[[Papilio Quick Links]]
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(:include Papilio Quick Links:)
to:
(:include Papilio_Quick_Links:)
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(:include Papilio Quick Links:)
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* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Papilio One ucf file]] - The user constraint file (ucf) defines all the FPGA pins for your Xilinx ISE projects.
* [[Papilio One FPGA pin to Wing Mappings]] - Use this chart to determine which FPGA pin is connected to what Wing position.
* [[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Papilio One Schematic]] - PDF version of the Papilio One Schematic.
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|Papilio One EAGLE files]] - EAGLE schematic and board design files.
to:
Added line 16:
[[Papilio Quick Links]]
Added lines 18-19:
* [[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Papilio One Schematic]] - PDF version of the Papilio One Schematic.
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|Papilio One EAGLE files]] - EAGLE schematic and board design files.
Added line 17:
* [[Papilio One FPGA pin to Wing Mappings]] - Use this chart to determine which FPGA pin is connected to what Wing position.
Added lines 14-16:
----
!!Quick Links
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Papilio One ucf file]] - The user constraint file (ucf) defines all the FPGA pins for your Xilinx ISE projects.
Changed lines 38-39 from:
The Butterfly One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.
to:
The Papilio One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.
Changed line 62 from:
The onboard SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at startup. Bitstreams are loaded to SPI Flash using the [[Papilio Loader]].
to:
The on-board SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at start-up. Bitstreams are loaded to SPI Flash using the [[Papilio Loader]].
Changed lines 67-68 from:
The first time the Butterfly One is plugged into the computer it will be necessary to install the FTDI device drivers. [[http://ftdichip.com/Drivers/D2XX.htm|Drivers can be downloaded from the FTDI website]].
to:
The first time the Papilio One is plugged into the computer it will be necessary to install the FTDI device drivers. [[http://ftdichip.com/Drivers/D2XX.htm|Drivers can be downloaded from the FTDI website]].
Changed lines 70-71 from:
When the Butterfly One is plugged into the USB port both channels will be detected and will show up under the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.
to:
When the Papilio One is plugged into the USB port both channels will be detected and will show up under the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.
Changed lines 76-77 from:
The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Butterfly One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.
to:
The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Papilio One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.
Changed line 89 from:
The Butterfly One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.
to:
The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.
Changed line 60 from:
---
to:
----
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---
to:
----
Changed lines 65-66 from:

---
to:
The Papilio One uses a [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FTDI 2232D]] USB chip which provides two channels over one USB connection. One of the channels is configured as a simple UART device and shows up as a virtual COM port. The other channel takes advantage of the MPSSE (Multi-Protocol Synchronous Serial Engine) functionality to implement a high speed JTAG channel for programming the [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan 3E]].
!!!Drivers
The first time the Butterfly One is plugged into the computer it will be necessary to install the FTDI device drivers. [[http://ftdichip.com/Drivers/D2XX.htm|Drivers can be downloaded from the FTDI website]].

!!!UART
When the Butterfly One is plugged into the USB port both channels will be detected and will show up under the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.

!!!JTAG
The Xilinx device is programmed using any application that can support the FT2232D MPSSE JTAG mode. The [[http://gadgetforge.gadgetfactory.net/gf/project/butterflyloader/|Papilio Loader]] is one such application.

!!!JTAG Programming Port
The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Butterfly One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.

TEMPORARY LIMITATION: In order to use the external JTAG port the FT2232D lines that are connected to the JTAG port need to be put into a HIGH-Z state. This has not been tested yet and will probably require a special application.

!!!EEPROM
Custom VID/PID and configuration data can be loaded into the provided EEPROM using the [[http://ftdichip.com/Resources/Utilities.htm#MProg|FTDI MProg]] application.

-
---
Changed line 27 from:
* I/O can be jumpered to support 1.2V, 2.5V, or 3.3V.
to:
* I/O can be set to support 1.2V, 2.5V, or 3.3V.
Changed line 29 from:
* 4M SPI Flash for design persistance.
to:
* 4M SPI Flash for design persistence.
Changed lines 52-53 from:
The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibily damaging the 2.5V voltage regulator.
to:
The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator.
Added lines 60-72:
---
!! Memory
The onboard SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at startup. Bitstreams are loaded to SPI Flash using the [[Papilio Loader]].
---
!! Communications

---
!! Misc
!!! Oscillator
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a Digital Clock Manager. The Spartan 3E provides 4 Digital Clock Managers.

!!! LED's
The Butterfly One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.
Changed lines 1-2 from:
!! Papilio One Hardware
!!! Overview
to:
! Papilio One Hardware
!! Overview
Changed lines 15-36 from:
!!! Specifications
* Power
** Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
** Power supplied by a power connector or USB.
** DC Input Jack
*** Input Voltage (recommended): 6.5-15V
* USB
** Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
** EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.
*Spartan 3E FPGA
** 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
** VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
** I/O can be jumpered to support 1.2V, 2.5V, or 3.3V.
*SPI Flash
** 4M SPI Flash for design persistance.
*Wings
** 48 bidirectional I/O lines which can be split up as:
*** 1 - 32 Bit Wing or
*** 3 - 16 Bit Wings or
*** 6 - 8 Bit Wings
** .1" spacing for compatibility with bread boards.
----
to:
!! Specifications
Added lines 17-37:
* Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
* Power supplied by a power connector or USB.
* DC Input Jack
** Input Voltage (recommended): 6.5-15V
!!! USB
* Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.
!!! Spartan 3E FPGA
* 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
* VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
* I/O can be jumpered to support 1.2V, 2.5V, or 3.3V.
!!! SPI Flash
* 4M SPI Flash for design persistance.
!!! Wings
* 48 bidirectional I/O lines which can be split up as:
** 1 - 32 Bit Wing or
** 3 - 16 Bit Wings or
** 6 - 8 Bit Wings
* .1" spacing for compatibility with bread boards.
----
!! Power
Changed lines 40-41 from:
* Power Selection
to:
!!! Power Selection
Changed lines 46-47 from:
* I/O Bank Power Selection
to:
!!! I/O Bank Power Selection
Changed lines 50-51 from:
* RPAR
to:
!!! RPAR
Changed lines 54-59 from:
* Power Jack

** Input: 6-15V DC
** Current: Draws up to 800mA
** Size: 2.1mm
** Polarity: Positive Tip
to:
!!! Power Jack

* Input: 6-15V DC
* Current: Draws up to 800mA
* Size: 2.1mm
* Polarity: Positive Tip
Changed lines 40-41 from:
!!!! Power Selection
to:
* Power Selection
Changed lines 46-47 from:
!!!! I/O Bank Power Selection
to:
* I/O Bank Power Selection
Changed lines 50-51 from:
!!!! RPAR
to:
* RPAR
Changed lines 54-59 from:
!!!! Power Jack

* Input: 6-15V DC
* Current: Draws up to 800mA
* Size: 2.1mm
* Polarity: Positive Tip
to:
* Power Jack

** Input: 6-15V DC
** Current: Draws up to 800mA
** Size: 2.1mm
** Polarity: Positive Tip
Changed line 37 from:
!! Power
to:
!!! Power
Changed lines 40-41 from:
!!! Power Selection
to:
!!!! Power Selection
Changed lines 46-47 from:
!!! I/O Bank Power Selection
to:
!!!! I/O Bank Power Selection
Changed lines 50-51 from:
!!! RPAR
to:
!!!! RPAR
Changed lines 54-59 from:
!!! Power Jack

* Input: 6-15V DC
* Current: Draws up to 800mA
* Size: 2.1mm
* Polarity: Positive Tip
to:
!!!! Power Jack

* Input: 6-15V DC
* Current
: Draws up to 800mA
* Size: 2.1mm
*
Polarity: Positive Tip
Added lines 37-59:
!! Power
The Butterfly One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.

!!! Power Selection

When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

!!! I/O Bank Power Selection

The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

!!! RPAR

The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibily damaging the 2.5V voltage regulator.

!!! Power Jack

* Input: 6-15V DC
* Current: Draws up to 800mA
* Size: 2.1mm
* Polarity: Positive Tip
Changed lines 17-31 from:
* Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
* Power supplied by a power connector or USB.
* DC Input Jack
** Input Voltage (recommended): 6.5-15VUSB\\
* Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.Spartan 3E FPGA
* 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
* VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
* I/O can be jumpered to support 1.2V, 2.5V, or 3.3V.SPI Flash
* Atmel [[http://www.atmel.com/dyn/resources/prod_documents/doc3638.pdf| AT45DB021D]] 2M SPI FlashWings
* 48 bidirectional I/O lines which can be split up as:
** 1 - 32 Bit Wing or
** 3 - 16 Bit Wings or
** 6 - 8 Bit Wings
* .1&quot;
spacing for compatibility with bread boards.
to:
** Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
** Power supplied by a power connector or USB.
** DC Input Jack
*** Input Voltage (recommended): 6.5-15V
* USB
** Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
** EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.
*
Spartan 3E FPGA
** 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
** VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
** I/O can be jumpered to support 1.2V, 2.5V, or 3.3V.
*
SPI Flash
** 4M SPI Flash for design persistance.
*Wings
** 48 bidirectional I
/O lines which can be split up as:
*** 1 - 32 Bit Wing or
*** 3 - 16 Bit Wings or
*** 6 - 8 Bit Wings
** .1" spacing for compatibility with bread boards.
Deleted lines 36-50:
!!! Resources
* Documentation - Quickstart Guides, User Guide, Pinouts
** [[Path:/gf/project/butterfly_one/wiki/|Project Wiki]]
* User Constraint Files (UCF) - Defines all pins and clock for Papilio One board.
** [[http://gadgetforge.gadgetfactory.net/gf/project/butterfly_one/frs/?action=FrsReleaseBrowse&amp;frs_package_id=17| File Repository]]
* Eagle PCB schematic and board files.
** [[Path:/gf/project/butterfly_one/scmsvn/?action=browse&amp;path=%2Ftrunk%2F| SVN repository]]
* Arduino/Wiring development environment to make Gadgets using Arduino compatible sketches.
** [[Path:/gf/project/wiringide/| Papilio Wiring/Arduino IDE]]
* Papilio/Butterfly Loader to make Gadgets using VHDL/Verilog with the free [[http://www.xilinx.com/support/download/index.htm| Xilinx Webpack IDE]].
** [[Path:/gf/project/butterflyloader/| Papilio/Butterfly Loader]]
* Sump Logic Analyzer to use the Butterfly One as a logic analyzer.
** [[Path:/gf/project/lax/| Sump Logic Analyzer]]
* Complete list of Wings to add peripheral functionality without soldering or breadboarding.
** [[Path:/gf/products/?action=ProjectTroveBrowse&amp;_trove_category_id=312| All Wings]]
Changed line 3 from:
The Butterfly One is a Gadget development board based on the
to:
The Papilio is a FPGA development board based on the
Changed lines 6-18 from:
programmer, 4 power supplies, and a power connector. It provides
everything needed to make Gadgets using
[[Path:/gf/project/wiringide/|
Arduino compatible sketches
]] or standard VHDL/Verilog.
Hardware can be added without any soldering or bread boarding
using the provided &quot;[[http
://www.gadgetfactory.net/index.php?main_page=index&cPath=4|Wing]]&quot;
slots. The Butterfly One places the focus on bringing Gadgets to
life rather than reading through datasheets.


The Butterfly
One can be purchased in the online store:\\
[[http://www
.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=18&amp;zenid=hdn32dl8jp4bi2nsdasbkp46r4|Butterfly One with 250K Xilinx Spartan 3E]]\\
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=25|Butterfly One with 500K Xilinx Spartan 3E]]
to:
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning [[Digital Electronics]].


The Papilio can be bought from the [[http://www.gadgetfactory.net | Gadget Factory store.]]

The Papilio One comes in two sizes
:
* [[http://www.gadgetfactory.net/index.php?main_page=product_info&cPath=1&products_id=18 | Papilio One 250K]] - $49.99 in the store now.
* [[http://www
.gadgetfactory.net/index.php?main_page=product_info&cPath=1&products_id=25 | Papilio One 500K]] - $74.99 in the store now.
Changed lines 37-38 from:
----!!! Resources
to:
----
!!! Resources
Changed lines 1-2 from:
!! Overview
to:
!! Papilio One Hardware
!
!! Overview
Changed line 20 from:
!! Specifications
to:
!!! Specifications
Changed line 37 from:
!! Resources
to:
----!!! Resources
Changed lines 35-50 from:
* .1&quot; spacing for compatibility with bread boards.
to:
* .1&quot; spacing for compatibility with bread boards.
!! Resources
* Documentation - Quickstart Guides, User Guide, Pinouts
** [[Path:/gf/project/butterfly_one/wiki/|Project Wiki]]
* User Constraint Files (UCF) - Defines all pins and clock for Papilio One board.
** [[http://gadgetforge.gadgetfactory.net/gf/project/butterfly_one/frs/?action=FrsReleaseBrowse&amp;frs_package_id=17| File Repository]]
* Eagle PCB schematic and board files.
** [[Path:/gf/project/butterfly_one/scmsvn/?action=browse&amp;path=%2Ftrunk%2F| SVN repository]]
* Arduino/Wiring development environment to make Gadgets using Arduino compatible sketches.
** [[Path:/gf/project/wiringide/| Papilio Wiring/Arduino IDE]]
* Papilio/Butterfly Loader to make Gadgets using VHDL/Verilog with the free [[http://www.xilinx.com/support/download/index.htm| Xilinx Webpack IDE]].
** [[Path:/gf/project/butterflyloader/| Papilio/Butterfly Loader]]
* Sump Logic Analyzer to use the Butterfly One as a logic analyzer.
** [[Path:/gf/project/lax/| Sump Logic Analyzer]]
* Complete list of Wings to add peripheral functionality without soldering or breadboarding.
** [[Path:/gf/products/?action=ProjectTroveBrowse&amp;_trove_category_id=312| All Wings]]
Changed line 20 from:
<li>Power
to:
* Power
Changed lines 1-2 from:
to:
!! Overview
Added lines 18-35:
----
!! Specifications
<li>Power
* Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
* Power supplied by a power connector or USB.
* DC Input Jack
** Input Voltage (recommended): 6.5-15VUSB\\
* Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.Spartan 3E FPGA
* 32MHz oscillator that can be used by Xilinx's DCM to generate any required clock speed.
* VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
* I/O can be jumpered to support 1.2V, 2.5V, or 3.3V.SPI Flash
* Atmel [[http://www.atmel.com/dyn/resources/prod_documents/doc3638.pdf| AT45DB021D]] 2M SPI FlashWings
* 48 bidirectional I/O lines which can be split up as:
** 1 - 32 Bit Wing or
** 3 - 16 Bit Wings or
** 6 - 8 Bit Wings
* .1&quot; spacing for compatibility with bread boards.
Added lines 1-2:
Changed lines 4-15 from:
Xilinx Spartan 3E FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides
everything needed to make Gadgets using
[[Path:/gf/project/wiringide/|
Arduino compatible sketches]] or standard VHDL/Verilog.
Hardware can be added without any soldering or bread boarding
using the provided &quot;[[http://www.gadgetfactory.net/index.php?main_page=index&cPath=4|Wing]]&quot;
slots. The Butterfly One places the focus on bringing Gadgets to
life rather than reading through datasheets.
to:
Xilinx Spartan 3E FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides
everything needed to make Gadgets using
[[Path:/gf/project/wiringide/|
Arduino compatible sketches]] or standard VHDL/Verilog.
Hardware can be added without any soldering or bread boarding
using the provided &quot;[[http://www.gadgetfactory.net/index.php?main_page=index&cPath=4|Wing]]&quot;
slots. The Butterfly One places the focus on bringing Gadgets to
life rather than reading through datasheets.
Changed lines 17-18 from:
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=18&amp;zenid=hdn32dl8jp4bi2nsdasbkp46r4|Butterfly One with 250K Xilinx Spartan 3E]]\\
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=25|Butterfly One with 500K Xilinx Spartan 3E]]
to:
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=18&amp;zenid=hdn32dl8jp4bi2nsdasbkp46r4|Butterfly One with 250K Xilinx Spartan 3E]]\\
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=25|Butterfly One with 500K Xilinx Spartan 3E]]
Deleted line 0:
Added line 1:
Changed lines 12-13 from:
life rather than reading through datasheets.</p>
to:
life rather than reading through datasheets.
Changed line 17 from:
<a href="http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=25">Butterfly One with 500K Xilinx Spartan 3E
to:
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=25|Butterfly One with 500K Xilinx Spartan 3E]]
Changed lines 1-5 from:
The Butterfly One is a Gadget development board based on the Xilinx Spartan 3E FPGA (datasheet). It has 48 I/O lines, dual channel USB, integrated JTAG programmer, 4 power supplies, and a power connector. It provides everything needed to make Gadgets using Arduino compatible sketches or standard VHDL/Verilog. Hardware can be added without any soldering or bread boarding using the provided "Wing" slots. The Butterfly One places the focus on bringing Gadgets to life rather than reading through datasheets.

The Butterfly One can be purchased in
the online store:
Butterfly One with 250K Xilinx Spartan 3E
Butterfly
One with 500K Xilinx Spartan 3E
to:
The Butterfly One is a Gadget development board based on the
Xilinx Spartan 3E FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines
, dual channel USB, integrated JTAG
programmer
, 4 power supplies, and a power connector. It provides
everything needed to make Gadgets using
[[Path:
/gf/project/wiringide/|
Arduino compatible sketches]] or standard VHDL/Verilog.
Hardware can be added without any soldering or bread boarding
using the provided &quot;[[http://www
.gadgetfactory.net/index.php?main_page=index&cPath=4|Wing]]&quot;
slots. The Butterfly One places
the focus on bringing Gadgets to
life rather than reading through datasheets.</p>

The Butterfly One can be purchased in the online store:\\
[[http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=18&amp;zenid=hdn32dl8jp4bi2nsdasbkp46r4|Butterfly One with 250K Xilinx Spartan 3E]]\\
<a href="http://www.gadgetfactory.net/index.php?main_page=product_info&amp;cPath=1&amp;products_id=25">
Butterfly One with 500K Xilinx Spartan 3E
Added lines 1-5:
The Butterfly One is a Gadget development board based on the Xilinx Spartan 3E FPGA (datasheet). It has 48 I/O lines, dual channel USB, integrated JTAG programmer, 4 power supplies, and a power connector. It provides everything needed to make Gadgets using Arduino compatible sketches or standard VHDL/Verilog. Hardware can be added without any soldering or bread boarding using the provided "Wing" slots. The Butterfly One places the focus on bringing Gadgets to life rather than reading through datasheets.

The Butterfly One can be purchased in the online store:
Butterfly One with 250K Xilinx Spartan 3E
Butterfly One with 500K Xilinx Spartan 3E
  

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