AltOR32 OpenRISC ISA CPU
Overview
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project.
Quicklinks
Description
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project. Instructions & registers relating to Vector, floating-point, 64-bit extensions, MMU & Cache have been omitted. The aim of AltOR32 is to provide a simple 32-bit soft CPU architecture aimed at control applications that can fit in low-end FPGA technology. This architecture re-uses the OpenRisc GNU toolchain hence implements all instructions that cannot be disabled. Anything else is viewed as beyond the scope of this cut-down soft-CPU implementation.
Get started
- Build the ISE based project.
- Download to Papilio.
- You should be greeted with the bootloader via the serial port (115K,8N1).
- Select '' to upload code to internal blockRAM (the remainder that is, starting from 0x2000) using X-Modem protocol.
- Select <F> to flash a FPGA (.bin file to be generated using bit_to_bin.bat) to SPI flash
- Select <A> to flash an app image to remainder of SPI Flash.
- <E> is for flashing external memory, which the Papilio project does not make use of (but could if I ported it to the Papilio Plus!).
Two things you need:
- OpenRISC toolchain that you can download from the link above.
- Verilator [Optional]
An example app can be built by typing make in: altor32\fpga\papilio_xc3s250e\sw